publication order number: mmft2955e/d ? semiconductor components industries, llc, 2006 august, 2006 ? rev. 7 1 mmft2955e preferred device power mosfet 1 amp, 60 volts p ? channel sot ? 223 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. this new energy efficient device also offers a drain ? to ? source diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. the device is housed in the sot ? 223 package which is designed for medium power surface mount applications. features ? silicon gate for fast switching speeds ? the sot ? 223 package can be soldered using wave or reflow ? the formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die ? pb ? free package is available maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v ds 60 vdc gate ? to ? source voltage ? continuous v gs 15 drain current ? continuous drain current ? pulsed i d i dm 1.2 4.8 adc total power dissipation @ t a = 25 c derate above 25 c p d (note 1) 0.8 6.4 w mw/ c operating and storage temperature range t j , t stg ? 65 to 150 c single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 25 v, v gs = 10 v, peak i l = 1.2 a, l = 0.2 mh, r g = 25 ) e as 108 mj thermal characteristics thermal resistance, junction ? to ? ambient (surface mounted) r ja 156 c/w maximum temperature for soldering purposes, time in solder bath t l 260 10 c s stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. power rating when mounted on fr ? 4 glass epoxy printed circuit board using recommended footprint. 1 ampere, 60 volts r ds(on) = 300 m device package shipping ? ordering information MMFT2955ET1 sot ? 223 1000 tape & reel mmft2955et3 sot ? 223 4000 tape & reel d s g p ? channel preferred devices are recommended choices for future use and best overall value. http://onsemi.com MMFT2955ET1g sot ? 223 (pb ? free) 1000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 2 3 4 to ? 261aa case 318e style 3 a = assembly location y = year w = work week = pb ? free package 2955e = device code marking diagram and pin assignment 3 source 2 drain 1 gate 4 drain (note: microdot may be in either location) ayw 2955e
mmft2955e http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage, (v gs = 0, i d = 250 a) v (br)dss 60 ? ? vdc zero gate voltage drain current, (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 1.0 50 adc gate ? body leakage current, (v gs = 15 v, v ds = 0) i gss ? ? 100 nadc on characteristics gate threshold voltage, (v ds = v gs , i d = 1 ma) v gs(th) 2.0 ? 4.5 vdc static drain ? to ? source on ? resistance, (v gs = 10 v, i d = 0.6 a) r ds(on) ? ? 0.3 drain ? to ? source on ? voltage, (v gs = 10 v, i d = 1.2 a) v ds(on) ? ? 0.48 vdc forward transconductance, (v ds = 15 v, i d = 0.6 a) g fs ? 7.5 ? mhos dynamic characteristics input capacitance (v ds = 20 v, v gs = 0, f = 1 mhz) c iss ? 460 ? pf output capacitance c oss ? 210 ? reverse transfer capacitance c rss ? 84 ? switching characteristics (note 2) turn ? on delay time (v dd = 25 v, i d = 1.6 a v gs = 10 v, r g = 50 , r gs = 25 ) t d(on) ? 18 ? ns rise time t r ? 29 ? turn ? off delay time t d(off) ? 44 ? fall time t f ? 32 ? total gate charge (v ds = 48 v, i d = 1.2 a, v gs = 10 vdc) see figures 15 and 16 q g ? 18 ? nc gate ? source charge q gs ? 2.8 ? gate ? drain charge q gd ? 7.5 ? source drain diode characteristics (note 3) forward on ? voltage i s = 1.2 a, v gs = 0 v sd ? 1.0 ? vdc forward turn ? on time i s = 1.2 a, v gs = 0, dl s /dt = 400 a/ s, v r = 30 v t on limited by stray inductance reverse recovery time t rr ? 90 ? ns 2. switching characteristics are independent of operating junction temperature. 3. pulse test: pulse width 300 s, duty cycle 2%. typical electrical characteristics figure 1. on region characteristics figure 2. gate ? threshold voltage variation with temperature 10 8 6 4 2 0 10 8 6 4 2 0 v ds , drain?to?source voltage (volts) i d , drain current (amps) 20 v 15 v 10 v 8 v 7 v 6 v 5 v v gs = 4 v v gs(th) , gate threshold volts (normalized) 1.1 ?50 t j , junction temperature ( c) 0.7 0.8 0.9 1 0 50 100 150 v ds = v gs i d = 1 ma 1.2 t j = 25 c
mmft2955e http://onsemi.com 3 typical electrical characteristics r ds(on) , drain?to?source resistance (ohm s r ds(on) , drain?to?source resistance (ohms) r ds(on) , drain?to?source resistance (ohms) figure 3. transfer characteristics figure 4. on ? resistance versus drain current figure 5. on ? resistance versus gate ? to ? source voltage figure 6. on ? resistance versus junction temperature 8 v gs , gate?to?source voltage (volts) i d , drain current (amps) 6 4 2 0 10 8 6 4 2 0 v ds = 10 v ?55 c 25 c 100 c ?55 c 25 c 100 c ?55 c i d , drain current (amps) 0.6 0 0.5 0.4 0.3 0.2 0.1 0 2468 v gs = 10 v 100 c 25 c ?55 c 0.5 v gs , gate?to?source voltage (volts) 4 0.4 0.2 0.1 0 0.3 710131619 t j = 25 c i d = 1.2 a 0.5 t j , junction temperature ( c) 0.4 0.2 0.1 0 0.3 ?50 0 50 100 150 v gs = 10 v i d = 1.2 a forward biased safe operating area the fbsoa curves define the maximum drain ? to ? source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on a ambient temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. on semiconductor application note, an569, ?transient thermal resistance ? general data and its use? provides detailed instructions. switching safe operating area the switching safe operating area (soa) is the boundary that the load line may traverse without incurring damage to the mosfet. the fundamental limits are the peak current, idm and the breakdown voltage, bvdss. the switching soa is applicable for both turn ? on and turn ? off of the devices for switching times less than one microsecond. figure 7. maximum rated forward biased safe operating area d i , drain current (amps) 1 0.1 0.01 0.1 10 100 v ds , drain?to?source voltage (volts) 10 1 s dc 500 ms 1 r ds(on) limit thermal limit package limit 100 ms 20ms v gs = 20 v single pulse t a = 25 c
mmft2955e http://onsemi.com 4 figure 8. thermal response 1.0 0.1 0.001 1.0e?05 1.0e?04 1.0e?03 1.0e?02 1.0e?01 1.0e+00 r(t), effective thermal resistance t, time (s) 0.1 0.01 0.2 0.02 0.01 d = 0.5 single pulse (normalized) 0.05 r ja (t) = r(t) r ja r ja = 156 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) ? t a = p (pk) r ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+01 commutating safe operating area (csoa) the commutating safe operating area (csoa) of figure 10 defines the limits of safe operation for commutated source ? drain current versus re ? applied drain voltage when the source ? drain diode has undergone forward bias. the curve shows the limitations of i fm and peak v ds for a given rate of change of source current. it is applicable when waveforms similar to those of figure 9 are present. full or half ? bridge pwm dc motor controllers are common applications requiring csoa data. device stresses increase with increasing rate of change of source current so di s /dt is specified with a maximum value. higher values of di s /dt require an appropriate derating of i fm , peak v ds or both. ultimately di s /dt is limited primarily by device, package, and circuit impedances. maximum device stress occurs during t rr as the diode goes from conduction to reverse blocking. v ds(pk) is the peak drain ? to ? source voltage that the device must sustain during commutation; i fm is the maximum forward source ? drain diode current just prior to the onset of commutation. v r is specified at 80% rated bv dss to ensure that the csoa stress is maximized as i s decays from i rm to zero. r gs should be minimized during commutation. t j has only a second order effect on csoa. stray inductances in on semiconductor?s test circuit are assumed to be practical minimums. dv ds /dt in excess of 10 v/ns was attained with di s /dt of 400 a/ s. figure 9. commutating waveforms figure 10. commutating safe operating area (csoa) 15 v v gs 0 90% i fm dl s /dt i s 10% t rr t frr 0.25 i rm i rm t on v ds v f v dsl v r v ds(pk) max. csoa stress area s i , source current (amps) v ds , drain?to?source voltage (volts) 6 5 4 3 2 1 0 80 70 60 50 40 30 20 10 0 di s /dt 400 a/ s
mmft2955e http://onsemi.com 5 r g t v ds l i l v dd t p bv dss v dd i l(t) t, (time) figure 11. commutating safe operating area test circuit figure 12. unclamped inductive switching test circuit + ? + ? figure 13. unclamped inductive switching waveforms v r v gs i fm 20 v r gs dut i s l i v r = 80% of rated v dss v dsl = v f + l i ? dl s /dt v ds figure 14. capacitance variation with voltage 1000 800 200 400 600 0 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) c iss 1200 1400 1600 1800 c rss c oss c iss c oss c rss v gs 15 10 5 0 5 10 15 20 v ds v gs v ds t j = 25 c f = 1 mhz same devicet y as dut v in +18v v dd 10v 100k 0.1 f ferrite bead dut 100 2n3904 2n3904 47k 15v 100k v in = 15 v pk ; pulse width 100 s, duty cycle 10%. 1ma 47k figure 15. gate charge versus gate ? to ? source voltage figure 16. gate charge test circuit q g , total gate charge (nc) 0 10 3 7.5 13 20 v gs , gate?to?source voltage (volts) 9 8 7 6 5 4 3 2 1 0 t j = 25 c v ds = 48 v i d = 1.2 a
mmft2955e http://onsemi.com 6 package dimensions sot ? 223 (to ? 261) case 318e ? 04 issue l a1 b1 d e b e e1 4 123 0.08 (0003) a l1 c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 1.5 0.059 mm inches scale 6:1 3.8 0.15 2.0 0.079 6.3 0.248 2.3 0.091 2.3 0.091 2.0 0.079 soldering footprint* h e dim a min nom max min millimeters 1.50 1.63 1.75 0.060 inches a1 0.02 0.06 0.10 0.001 b 0.60 0.75 0.89 0.024 b1 2.90 3.06 3.20 0.115 c 0.24 0.29 0.35 0.009 d 6.30 6.50 6.70 0.249 e 3.30 3.50 3.70 0.130 e 2.20 2.30 2.40 0.087 0.85 0.94 1.05 0.033 0.064 0.068 0.002 0.004 0.030 0.035 0.121 0.126 0.012 0.014 0.256 0.263 0.138 0.145 0.091 0.094 0.037 0.041 nom max l1 1.50 1.75 2.00 0.060 6.70 7.00 7.30 0.264 0.069 0.078 0.276 0.287 h e ? ? e1 0 1 0 0 1 0 style 3: pin 1. gate 2. drain 3. source 4. drain *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mmft2955e/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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